This invention relates in general to a packaged structure and method for making this structure, and more specifically to a package for devices of microelectronics, optoelectronics, microelectromechanical systems, micro-fluidic systems, micro-total-analysis-systems, bio-chip and micro-opto-electro-mechanical systems.
As there is a tendency that the products are demanded to be lighter, smaller, and portable, the RandD trend of semiconductor, microelectronics, electronics and relative devices is toward miniaturization, higher integration, faster operation speed, and lower power consumption. Thus the packaging technology is required to provide devices and components to meet this trend. Among the packaging technologies, the wafer-level chip size packaging (WLCSP) or wafer-level chip scale packaging (WLCSP) is rather promising technology for fulfilling the miniaturization purpose, because the packaged CSP device size is only about 25% larger than the bare die size.
Due to the development of trend of aforementioned devices, the number of signal I/O (inputs and outputs) of device is increased, the density of interconnection is increased, and the line width of interconnection is reduced. Therefore, the surface mount technology (SMT) is developed in order to solve these problems. Such miniaturizing developments are developed from SOP, SOJ, SSOP, and to TSOP, and from QFP, LQFP, and to TQFP, etc. As the amount of the I/Os is keeping growth, the packaging size will be enlarged, and it is accompanied with many problems, such that non-wetting of soldering balls or the deformation/warpage of substrate. Reducing the packaged size as small as possible may solve these problems. Besides, the arrangement of I/Os location is moving from peripheral site only to all surface of the packaged device, it means there is more area to allocate the I/Os. The chip scale package (CSP) actually realizes these ideas.
Presently, there are over 50 kinds of chip-scale-package (CSP) products disclosed by over 16 semiconductor companies in the world. These CSPs are classified into four types base on the design concepts and package structures.
(1) Leadframe based CSPs: a package design that follows the concept of the LOC (lead on chip), of which the connection between the interposer and the dies is accomplished by wiring, and the area is reduced continuously until the size is achieved at the definition range of the CSP.
(2) CSPs with Rigid Substrate: there is a rigid substrate applied in between the bare die and the package housing structure, and it is used as a carrier; the material thereof mostly is a ceramics substrate or a rigid printed circuit board of polymer materials.
(3) CSPs with Flexible Substrate: the structure thereof is similar to the rigid substrate, but a soft substrate is used as a carrier instead; the common material is polyimide, and an elastomer is inserted between the die and the substrate in order to decrease the effect of the stress upon the devices; an arrangementxe2x80x94an area arrayxe2x80x94is used for rearranging the I/Os on one side of the soft carry board that opposite to the side without dies contacted thereon.
(4) Wafer-level CSPs: the external I/Os of the made devices thereof are fan-in arranged; the size of the made devices are almost the same as the size of the dies; the carrier substrate is usually a wafer; it is connected with the dies by the technique similar to that of the flip-chip, and no encapsulation process is needed, then the I/Os are rearranged as an area array on the side with dies thereon.
Besides, the flip-chip technology by die bonding or attaching chips with metal bumps onto substrate carrier, and underfilling polymer materials between the die and substrate spacing thereafter is invented to reduce the package size.
Again, as the increasing complexity of portable electronic systems, such as, mobile phone, PDA, and portable computer, etc., more functions are integrated into a single chip, thus the concept of system-on-chip (SoC) is generated. However, there are many difficulties of developing SoC, especially integrating various functions, of each are uniquely designed, having various data base, design rule, and intellectual properties (IP) from various companies, that usually takes a lot of time for integration and transformation. To have a SoC may be an ultimate goal, combining the state-of-the-art WLP and CSP technologies can make hybrid packaged ICs in rather small forms. In the other words, assembling two or more bare dies into various kinds of multichip modules (MCMs) and with final outlooks like a single packaged device, i.e., the system-in-a-package (SiP) approach. Especially the SiP approach may enable the dies to be tested in wafer-level, for example, the known good die (KGD) process. In the case of MCM and SiP, the wafer-level testing are further proceeded in order to promote the packaging yield and save the dispensable packaging cost. For the customers, by means of SiP, the cost and time for development of a system product are reduced, the performance are optimized as well.
According to the present situation of portable electronic devices, a lot of passive components are packaged into device together, these passive components or elements are like resistors, capacitors, and inductors. In order to shrink the size of packaged devices, two ways have been proposed, they are the passive devices made by low temperature co-firing ceramics (LTCC) process, and the integrated thin film passive devices (IPD). First of all, by using the conventional screen printing and sintering technology, the minimum feature size made by LTCC is around or above 50 ?m, and is hard to be controlled. It causes the made RF circuits can hardly show good high frequency performance in a repeatable and precise manner. Secondly the IPD is made normally by depositing and patterning the resistors, capacitors, and inductors materials on substrates, where these substrates are usually the wafer forms. The made RF module based on IPD will have smaller size and higher precised performance.
FIGS. 1a and 1b show an RF module in IPD (Integrated Passive Devices) format, fabricated by thin film process disclosed by Intarsia in the United States at the Systems Design Magazine on August 2000 and December 2000, respectively (see the reference materials [1], [2] and [3]). FIG. 1a shows the steps of forming the electrode. FIG. 1b shows the said RF module whose passive devices like inductor, capacitor, and resistor are made by the standard thin film process of IC industry. The formation of the thin film resistor, as shown in FIG. 1a, a resistance layer 11 is deposited and defined on the glass substrate 10, then a first conductive layer 12 is deposited and defined by etching or lift-off process. The first conductive layers 12 which are made onto both end of the resistance layer 11 are electrodes of resistor R. Thereafter a second isolation layer 15 is deposited and defined. Again, the formation of the integrated passive device is shown in FIG. 1b; a resistant layer 11 is deposited and defined on the substrate 10 firstly, then a first metal pattern 12 is deposited and defined by etching or the lift-off method. The first metal pattern 12 is the electrodes on the both ends of the resistor R. Then, a first dielectric layer 13 and a second metal pattern 14 is deposited, thus a capacitor C is formed by the first dielectric layer 13 and two patternsxe2x80x94which are above and under thereof respectivelyxe2x80x94the first metal pattern 12 and the second metal pattern 14. Afterwards, a second dielectric layer 15 is formed onto the resistor R and the capacitor C for isolation. The second dielectric layer 15 is required to be thick enough in order to cover the devices and to be applied uniformly onto the substrate. Then a lead guide hole is defined on the second dielectric layer 15, a buffer layer (or adhesion layer) 16 is formed for advancing the interconnection and the adhesion to the follow-up conductive layer 17. Then, while a third metal pattern 17 is being defined, the inductor L, and the metal pad of the solder bumper for interconnecting with the follow-up package are fabricated simultaneously.
The device is packaged by applying the technique of die level package, as shown in FIGS. 1c and 1d. As shown in FIG. 1c, a solder ball 18 is grown onto the conductive layer initially, then it is bonded with polymer substrate seal-lid 19 by the flip-chip bonding method, and the underfill 20 is made; thus the reliability of the solder joint is enhanced. Alternately, as shown in FIG. 1d, an active device 21 is bonded onto the glass substrate 10 by the flip-chip bonding method, then a solder ball 18 is grown onto the conductive layer, next it is bonded with macromolecule substrate seal-lid 19 by the flip-chip bonding method, and the underfill 20 is proceeded. The step of underfill is used in such package method, wherein the material thereof can flows naturally since the capillarity; although the reliability of the solder joint is enhanced, since the flow and the flow time thereof are uneasy to be controlled accurately, thus the quality rate of the process would be lowered; and the production capability would be influenced by the long solidification time thereof would.
Besides, the MOST (microspring contact on silicon technology) disclosed by the FormFactor Company in America are applied to the wafer-level chip scale package. By using this technique, it is provided with the chip-level interconnects on the wafer. The whole processes of the later packaging are accomplished at the wafer stage by using the MOST, such as the corresponding packaging, the burn-in process, the high-speed testing and the component appearance assembly. The micro-spring is applied as the internal interconnection, and it is the main, basic function of the MOST. Therefore, no leadframe, no molding process is required by using this technique, thus the cost thereof is lower than conventional chip-scale package. Since the micro-spring is provided with well compliance, so it is not required as the solder-bump flip-chip on board that needed to be applied with underfill process. Besides, the chip applied with MOST for the chip process are provided for burn-in and high-speed testing on the wafer-level state. The micro-spring consists of: the core is made of gold line, and then there is a conductive layer of nickel (or nickel alloy) coating or plating onto the surface; the outline thereof likes an PbSn solder paste is applied to the soldering point of the printed circuit board (PCB) by the screen printing method, and then the chip having the micro-spring applied as a connection pin is fetched onto the PCB exactly by a fetching apparatus that confronts automatically. After the surface adherence by the SMT reflow technique, a perfect solder-joints are formed. Various sockets are fabricated onto the PCB by the micro-spring, and then the whole PCB becomes a system integration platform. Besides, the structure of the sockets is capable of pitch transferring, and the requirements for high-density PCB by the whole package structure are lowered; thus, the package cost is reduced efficiently. Nevertheless, this technique is not practically used presently.
Microelectromechanical systems (MEMS) or Microsystems, by their nature, contains sensors, actuators, and peripheral electronics, require application specific packaging. For packaging of the MEMS devices, there are several requirements need to be fulfilled. Because the MEMS device is a three-dimentional structure, this structure has to be protected during the packaging process. MEMS normally comprise a wide variety of different functionalities, each functional elements are integrated either monolithically or hybrid, while the signals interface among each function elements and surrounding physical world has become very challenges. So most of MEMS devices cannot be packaged just as what semiconductors and microelectronics do by using the above-mentioned technologies.
However, if the knowledge and infrastructures of CSP, Filp-chip, MCMs, WLCSP, SiP technologies are applied to package MEMS devices, then progress of packaging technology for MEMS will be accelerated. Regarding to this viewpoint, there are key issues: one is how to make the signal transmission line inside the devices fabricated by the WLCSP method to be coordinated with the peripheral electronics. In other words, how to make signal transmission line or interconnection line crossing the said interface; another one is how to protect the fragile MEMS microstructures without damage during packaging.
Moreover, considering the state-of-the-art CSP, Filp-chip, MCMs, WLCSP, SiP technologies, especially from the experience of semiconductor packaging, the underfill process still remains very challenging in terms of cost, repeatability, quality control, and reliability.
In conclusion, based on micromachining, filp-chip and MCM technologies, a new technology for packaging microsystem devices with a small form factor is disclosed, and this approach is promising for making devices of system-in-a-package format. By using this disclosed technology and the concept of the system-in-a-package (SiP), the present invention provides a new structure for wafer-level-system-in-a-package (WLSiP) and the manufacturing method thereof This invention is applied to making package structure for devices of microelectronics, optoelectronics, microelectromechanical systems, micro-fluidic systems, micro-total-analysis-systems, bio-chip, and micro-opto-electro-mechanical systems. The process thereof is integrated with thin and thick film processes, the chip-scale packaging and flip-chip technologies, etc., and it is proceeded with a variety of wire-bonding, solder ball fabrication and solder pad in order to accomplish the external interconnection between the devices. And, the wafer-level packaging structures of the package interfaces of corresponding devices are completed during the wafer stage. The design for wafer-level testing and burn-in can also be integrated by technology of present invention for further reduction of the production cost of the devices.
Accordingly, it is an object of the present invention to provide a way to package devices of Microsystems. Therefore a package structure in system-in-a-package format is invented.
According to the new package structure of the invention, the package structure can consist elements and devices of plural functions, then the said package structure is a device and apparatus in system-in-a-package (SiP) format. Additionally, the method for making the said package structure is a wafer level approach process technology, in this case, the said package structure is a device and apparatus in wafer-level-system-in-a-package (WLSiP) format.
Another object of the present invention is applying the probes and probe cards with equipments to directly measure the system level parameters and performance corresponding to the said package structure, therefore the wafer level testing and wafer level reliability testing can be realized.?
To accomplish the above objects, substrates with integrated and assembled functional elements, and electrical conduction lines and interconnections can be aligned and pre-bonded to become a substrate of a stack of substrates. Microstructures of interposers, micro-joints, and micro-springs can act as the elements to form pre-bonding interface, the stress and impact buffers, and the alignment aids. Fluidic encapsulating materials can be guided and flown into the specified area inside the package structure via through-holes on the top substrate of the said stack of substrates. Thereafter, the solidification of encapsulating materials can be done with the heat inside a chamber with vacuum environment or ambient inert gas.
To accomplish the above objects, the said package structure is provided with both fan-out and fan-in formats of electrical interconnections, electrical conductive lines, heat-transferring paths and heat dispatching paths among the said package structure and other discrete devices; the pitch between each pair of I/O are designed, changed and made according to different application needs; the electrical signal are routed and arranged by making multilayer of electrical interconnections and insulating layers in order to make complex three-dimensional electrical interconnection structures thereof the said redistribution process. Additionally, wherein the electrical interconnection and signal I/O contacts inside the said package structure among different functional elements and dies are formed by bonding metal wires, depositing metal lines, plating metal lines, soldering, making conductive polymer and making bumping process of filp-chip technology.
To accomplish the above objects, the said package structure can be provided with the optical interconnection and signal I/O contacts of the said package structure for enabling free space optical communications.
To accomplish the above objects, the solidified and encapsulated bonded substrate can be divided into the individual packaged devices from the said package structure by using normal die separation technologies in semiconductor industry.
To accomplish the above objects, an example of the RF system-in-a-package device for wireless communication is cited in order to show the applications to the fabrication of the new package structure in accordance with the present invention. A substrate and a lid substrate are fabricated firstly, the sealing interface is accomplished by aligning, pre-bonding, and encapsulating steps.
Thus, the packaging is completed, and a package of the RF system-in-a-package device consisting of active and passive elements for wireless communication is provided.
The above objectives and advantages will become more apparent with explanation of the accompanying drawings.